The most valuable memory Samsung makes right now is not the one everyone is fighting over.
Buried in the company's own earnings is a fact that should reorder how the industry thinks about the AI buildout: the plain DRAM now earns fatter margins than the high-bandwidth memory strapped to every frontier GPU. Bernstein's numbers put conventional DRAM prices up roughly 4.5x from Q3 2025 to Q2 2026 while HBM stayed nearly flat—leaving commodity DRAM generating about twice the revenue and nearly three times the gross margin of HBM.
Samsung confirmed it. Non-HBM DRAM margins now exceed HBM's, with the gap expected to "narrow sharply" in 2027—which is the polite way of saying the HBM price increases are locked in and coming.
That single inversion explains why the shortage Jensen Huang keeps calling "multi-year" will not self-correct. The three companies who make the exotic memory AI depends on are structurally disincentivized from making more of it, because the boring stuff pays better per wafer today.
The three companies who make the exotic memory AI depends on are structurally disincentivized from making more of it, because the boring stuff pays better per wafer today.
Last week the story was scarcity and price: Bernstein's forecast that HBM triples 2 to 2.5x next year, Huang's Seoul warning that shortages persist for years, the SK hynix alliance locking in supply. This week the story got worse, because scarcity turned into a reliability problem.
At Hot Chips 2026, Micron Fellow Raghu Sriramaneni put a number on it. Citing Meta's Llama 3 data, he said HBM failures accounted for roughly 17% of unintended training interruptions.
Read that again. According to Micron's Llama 3 data, HBM accounted for roughly 17%—about one in six—of unintended training interruptions.
This reframes everything. You can pay the 2-2.5x markup, win an allocation from the three-maker oligopoly, and still lose runs—because the thing you paid a premium for reportedly accounts for a meaningful share of training interruptions.
And the physics is moving the wrong direction. Sriramaneni noted that accelerator compute performance roughly triples every two years, while HBM bandwidth grows less than twofold over the same window. The gap between what the chip can do and what the memory can feed it is widening, not closing.
The package itself tells the story. Micron reportedly pointed to a latest-generation part integrating two GPUs with eight 12-layer HBM4 stacks, where memory occupies roughly 90% of the semiconductor area—more than eight times the space taken by the actual GPUs.
The compute die everyone associates with an AI accelerator is now a rounding error on the substrate. The chip is mostly memory, and the memory is the failure point.
Then there is the wafer math that guarantees the squeeze holds. Producing the same capacity in HBM requires roughly three times as many wafers as standard DDR5. So every unit of HBM the makers commit to consumes triple the fab capacity of the higher-margin commodity product they'd rather sell.
Stack those facts and the incentive structure is brutal. The suppliers earn more on DDR5, HBM burns three times the wafers, HBM breaks one in six training runs, and demand for it is inelastic because there is no substitute. A cartel of three has no reason to spend scarce capacity fixing fault rates on a product that already sells out and pays less than the alternative.
Now trace the cost through Nvidia and the reason hyperscalers should be nervous becomes arithmetic. Because HBM is packaged inside the GPU, Bernstein estimates Nvidia must amplify HBM's cost increase by roughly 4x when passing it to customers—simply to hold its 75% gross margin.
That amplification is what turns a memory shortage into a capex event. Combined with rising conventional DRAM and NAND, Bernstein sees hyperscaler capital expenditure climbing about 30%.
Nobody slows down. The competitive dynamics won't allow it—the clouds keep spending. But Bernstein is explicit that a "cost rebalancing" is now unavoidable, and that weaker players get squeezed out in the process.
Here is where the two ends of the scaling curve meet and pinch. On one side, compute keeps tripling while memory bandwidth lags, so runs get more fragile as they get bigger. On the other, the memory that gates those runs gets more expensive and stays allocation-locked.
Scaling economics degrade at both ends at once—reliability erodes and cost inflates simultaneously—and the only defense is supply security you had to sign years ago.
That is what the SK hynix relationship actually buys. SK hynix reportedly supplies an estimated 50% to 70% of Nvidia's HBM4, per a UPI report, a level of single-vendor concentration that is unusual in semiconductors and reflects the reality that only three companies can make HBM4 at leading-edge yield at all.
Huang's Seoul chicken-and-beer diplomacy was not networking. It was Nvidia converting scarcity into scheduling discipline—multi-year volume commitments across several GPU generations, negotiated at the exact moment demand compounds.
Now ask who cannot sign that contract. 2026 HBM capacity from all three makers is reportedly already fully locked by downstream customers, with some allocations reserved out to 2028.
An undercapitalized chip startup does not get a chimaek dinner with Chairman Chey. It gets whatever spot allocation the three makers can spare from customers who committed years and billions in advance—which, given that the makers would rather sell DDR5 anyway, is close to nothing.
That is the squeeze, stated plainly. The players with SK hynix-style multi-generation locks survive; everyone dependent on spot allocation from a three-maker oligopoly that prefers commodity DRAM gets starved out first. The barrier to competing with Nvidia is no longer just design talent or software—it's whether you secured memory before the window closed.
The reliability angle sharpens this further. A hyperscaler with a supply contract can absorb a 17% interruption rate as an engineering problem, throwing redundancy and checkpointing at it. A startup renting scarce, expensive, failure-prone memory on the spot market absorbs it as an existential cost.
One place this repricing already shows up in shipping hardware: the trimmed Rubin configurations we flagged in prior weeks. Reports had the Vera Rubin NVL72's SOCAMM capacity dropping from roughly 55TB to about 28TB, with most systems using 96GB modules instead of the expected 192GB.
Huang confirmed the shape of it. He insisted Nvidia will keep using HBM heavily but must use memory "more wisely" under supply constraints—and the reduction reportedly lands on the CPU's LPDDR5X, not the GPU's HBM4, which holds capacity.
Because SOCAMM is slot-based, the cuts are framed as an upgradeable initial configuration rather than a permanent ceiling. But the framing matters less than the fact: Nvidia is trimming memory on its flagship platform to make its allocation stretch. If the company with 50-70% of SK hynix's HBM4 is rationing, everyone below it is rationing harder.
The bull case says this cycle breaks the industry's historical boom-bust curse—that long-term supply agreements, unprecedented wafer constraints, and insatiable AI demand have finally smoothed the violent swings. All three makers now run gross margins above 70%.
That may be true. But a broken cycle that permanently favors the incumbents is not good news for the AI market broadly—it's good news for exactly three companies and the handful of buyers big enough to pre-book them.
Huang can call it multi-year. What he's really describing is a structural transfer of pricing power to the memory oligopoly, at the precise moment the product they sell has become both the biggest cost line and the most common reason your training run dies. The suppliers can fix the fault rate or sell more DDR5. They have already told you which one pays better.