Seventy-two GPUs. Seventy-two GPUs. That is the number both NVIDIA and AMD landed on for their next-generation scale-up domain, and both wired it with roughly 3.6 TB/s of scale-up bandwidth per GPU. Not close. Identical.
On the Monday afternoon of Hot Chips 2026, in the GPU session that reportedly ran from 4:45 to 6:45 PM, four talks came back to back: NVIDIA's Rubin, then AMD's MI400 architecture, then AMD's MI400 system architecture, then Intel's Crescent Island. Each one opened on the same justification. Agentic AI.
NVIDIA called it "the most complex workload it has ever targeted." AMD framed its entire stack around 10-trillion-plus-parameter agentic and reasoning models. Intel opened with "a data center GPU purpose-built for agentic AI inference." Three companies, one phrase, one shared premise: the workload has changed enough that the rack must be redesigned around it.
Three companies, one phrase, one shared premise: the workload has changed enough that the rack must be redesigned around it.
That is where the convergence ends. Read the actual architectural disclosures and the three vendors are building three different things, and the differences decide how AI hardware gets bought for the next three years.
Start with what NVIDIA and AMD built, because they built the same machine. Vera Rubin NVL72 ties a 72-GPU scale-up domain with 3.6 TB/s of all-to-all bandwidth per GPU over sixth-generation NVLink. AMD's Helios rack holds 72 GPUs, and each MI455X reportedly pushes 3.6 TB/s across 72 UALoE lanes. Same GPU count. Same scale-up figure. Same thesis about long agentic context blowing past 400k tokens and straining hardware tuned for short prompts.
AMD even gave us the physical rack. A 44OU ORW-HPR chassis packs 18 compute trays and six switch trays, with blind-mate QD liquid cooling, redundant power supplies, and a 50V DC busbar. Two 512-port switch ASICs delivering 10.8 TB/s per direction. This is a monolith — 2.9 exaflops, 31 TB of HBM4, 72 GPUs wired into one switched fabric that reportedly gives every GPU shared load/store access across the whole pod.
The important thing about a monolith is that it is sold as one thing. You do not buy a Helios GPU and slot it next to someone else's switch. You buy the chassis, the busbar, the compute trays, the switch trays, the Fabric Manager control plane, and the RAS stack as a single indivisible unit.
AMD is explicit that it is a full-system company — CPUs, GPUs, networking, and finished systems, co-designed because "AI infrastructure now has to be co-designed across those pieces." That is a virtue on stage. It is a lock-in at the purchase order.
AMD knows this, which is why its second-source argument is baked into the silicon. UALoE runs "on open Ethernet and ESUN standards, and on (often) Broadcom switches, rather than on a closed fabric" — a deliberate contrast to NVLink. The pitch is that you can second-source the switch even inside an AMD rack.
But look at where the boundary actually falls. The Fabric Manager runs as a three-node cluster on the switches. Confidential computing spans EPYC, the MI455X, and the Pensando NIC. Virtual pods, RAS coordination, and fault rebalancing across five-of-six switch trays are all AMD's control plane. Open Ethernet at the transport layer does not make the rack mix-and-match — you still validate one vendor's fabric, one vendor's RAS, one vendor's orchestration as a single purchase.
So the second-source story is real at the switch ASIC and fictional at the rack. The unit of sale is the rack, and below the rack boundary there is no competitor to drop in. That is the same trap NVLink sets; AMD's is just built on Ethernet.
This is the fight NVIDIA and AMD have decided to have with each other: who owns the liquid-cooled 72-GPU socket, and whether the buyer's fabric is called NVLink or UALoE. It is a real fight. It is also a fight where the buyer loses second-sourcing below the rack no matter who wins.
Then Intel presented last, and conceded the fight entirely.
Crescent Island is a 350W air-cooled PCIe card. Not a rack. Not liquid-cooled. Not a scale-up domain. It ships branded at 160GB of LPDDR5X, with ODMs free to build cards up to 480GB, connected via PCIe Gen5 x16 over an open switch fabric to a Xeon head node.
The refusal is deliberate, and Intel showed its reasoning on one slide. Weights held reportedly grew about 7x from Llama 2 70B to Kimi K2 1T, while bytes read per token fell about 4x. Capacity and bandwidth have decoupled.
That decoupling is the whole argument. Decode for these mixture-of-experts models is KV-cache-bound; what you need is enough memory to hold the weights and the cache and enough sessions on one card, not the enormous all-to-all bandwidth a training monolith is built to deliver. Intel's own framing: hold FP8 weights and KV cache on a single card, run longer context and more concurrent agents, with fewer GPUs.
If that read is right, the largest pool of agentic inference spend never enters a rack at all. It stays in air-cooled PCIe slots, in existing data center footprints, priced on memory-capacity-per-watt. And you can buy one card. Or a thousand cards from different ODMs at 480GB each. There is no rack SKU to validate as one indivisible thing.
That is the split that actually matters, and it is not NVLink versus UALink. It is whether agentic inference budgets consolidate into rack-scale lock-in or fragment back into commodity servers.
Intel completes the picture with Diamond Rapids, the 2027 Xeon. Up to 256 cores, a unified memory fabric, 128 lanes of PCIe Gen6 and CXL 3.0. That makes Xeon the neutral orchestration host — the head node that sits above heterogeneous inference cards from anyone, over an open switch fabric, rather than inside one vendor's proprietary pod.
Intel's software choices point the same direction. Crescent Island supports vLLM, SGLang, llm-d, and — pointedly — NVIDIA Dynamo, "so agents run across heterogeneous infrastructure without code changes." That is not a stack built to lock you in. It is a stack built to be dropped into someone else's estate.
The consequence for procurement is stark. A rack-scale bet forces the buyer to validate an entire vendor's fabric, control plane, and RAS stack as a single purchase, killing the mix-and-match second-sourcing that kept prior GPU generations competitively priced. The PCIe card bet preserves it.
Which is why NVIDIA and AMD structurally cannot win the fight Intel picked. Their entire architecture — the value, the margin, the differentiation — lives in the 72-GPU scale-up domain and the fabric that binds it. Selling density in an air-cooled PCIe slot means giving up exactly the thing they built the rack to sell.
That does not mean Crescent Island wins. Intel still would not disclose its memory bandwidth on a part supposedly months from shipping, and ROCm-versus-CUDA aside, the software maturity question hangs over the whole thing. Whether a 350W air-cooled card wins sockets comes down to real tokens-per-watt results on hardware that has not shipped.
But the strategic geometry is clear. Two of the three vendors are fighting over the same liquid-cooled socket, and both need agentic inference budgets to consolidate into racks for that fight to matter. The third bet the largest pool of that spend never enters a rack.
Three companies said "agentic AI" and redesigned the rack. Only one of them redesigned it by deciding not to build one.