Here is a contradiction worth sitting with. Jensen Huang stood in Seoul this month and called the memory shortage "a structural industry problem" that will last years, warning HBM prices won't fall anytime soon. And yet the same company he runs is quietly testing a flagship GPU with less HBM than it originally promised.
Both things are true, and the tension between them is the whole story.
Nvidia—the most cash-rich buyer in AI, the company whose GPUs define the era—is reportedly testing a Rubin Ultra with as little as 192GB of memory. That is a startling number against the 1TB HBM4E concept the company floated for the same chip not long ago.
Last issue, we tracked the Rubin Ultra trim as an emerging fact: the specs were "in flux," per TrendForce, and Nvidia was weighing 8-high HBM4E against 12-high HBM4. This week we can supply the causal engine behind the trim, and it is not the one the spec sheets suggest.
The obvious explanation is scarcity. HBM is hard to make—16-layer stacks, TSV through-silicon vias, yields that ramp slowly—and only three firms, Samsung, SK hynix, and Micron, can mass-produce HBM4 at all. Their entire 2026 HBM output is already locked up, some of it booked to 2028.
But scarcity alone doesn't explain why the suppliers won't simply pour more wafers into the thing everyone is desperate for. The answer is that they make more money not doing so.
Follow the money upstream and the picture inverts. From Q3 2025 to Q2 2026, per Bernstein's estimates, commodity DRAM prices rose roughly 4.5x while HBM prices stayed nearly flat. By 2026, commodity DRAM reportedly earns about 2x the per-wafer revenue and close to 3x the gross margin of HBM, per Bernstein's estimates.
Read that again. The boring stuff—server DDR5, ordinary DRAM modules—now out-earns the exotic, strategic product that the entire AI buildout supposedly depends on.
According to Samsung's own earnings filing, non-HBM DRAM margins have already surpassed HBM, and the company reportedly expects the gap to widen.
Think about what that does to a memory maker's incentives. Every wafer diverted to HBM earns half the revenue and a third the margin it would earn as commodity DRAM. The strategic product has become the low-margin product.
The strategic product has become the low-margin product. The three-maker market has a rational reason to starve the very component the AI boom needs most.
So the three-maker market has a rational reason to starve the very component the AI boom needs most. Not out of malice—out of arithmetic. The bottleneck is not a temporary mismatch that the market will self-correct; it is a profit-maximizing equilibrium the suppliers have every reason to preserve.
Bernstein's own forecast quietly admits this. HBM prices are expected to rise 2 to 2.5x next year—meaningful, but well short of the 3x it would take to close the gap with commodity DRAM. The suppliers are letting HBM catch up slowly, on their own terms, extracting pricing power without ever tipping the incentive back toward flooding the market.
That is the seller's market Nvidia walked into. And it explains the Rubin Ultra diet in a way "shortage" never could.
Look at the engineering logic once the constraint becomes HBM dies rather than GPU performance. Eugene Investment's Injun Son puts hard numbers on it: for the same DRAM material input, assembling 12 stacks instead of 16 raises HBM unit output about 33%, and dropping from 12 stacks to 8 boosts output roughly 50%.
Fewer stacks per GPU also means lower defect rates and shorter lead times. So a leaner memory config isn't a compromise Nvidia grudgingly accepts—it's the only way to ship more accelerators from a fixed supply of dies.
That reframes the trim entirely. Nvidia isn't rationing memory because it can't afford it. It's rationing memory because the physical supply of dies, not its own design ambition, now dictates how many chips reach the market.
The performance cost is real and quantifiable. If 12-stack HBM4E qualifies on schedule, Rubin Ultra's I/O could hit 14–16 Gbps; fall back to HBM4 and it settles at 11–12 Gbps. Nvidia is choosing shipment volume over peak bandwidth—an unusual admission from a company whose entire brand is "more."
And it is not alone. AMD's MI400 is reportedly coming in both 8-stack and 12-stack HBM4 versions. SemiAnalysis reported Nvidia already halved the LPDDR5X in its Vera Rubin NVL72 platform, from 54TB to 27TB. The "despec" has spread from HBM to the whole rack.
Here is the uncomfortable structural point that lands underneath all of it. When commodity DRAM out-earns the strategic product in a three-supplier market, the party that controls wafer allocation—not the party that designs the chip—decides what AI hardware actually ships.
BusinessKorea put it plainly: the success of the next-generation AI race now hinges on securing a memory supply chain, not on chip design capability. Nvidia can architect a 1TB monster all it likes; if the dies don't exist, the chip doesn't ship.
This is why the phrase "seller's market" undersells what's happening. A normal shortage is self-correcting—high prices pull in capacity until the gap closes. This one is self-reinforcing, because the highest-margin use of a wafer is the one that does nothing to relieve the HBM bottleneck.
The earnings math confirms where the power sits. Son reportedly projects next year's HBM operating profit at Samsung and SK hynix to jump 539% and 286% year-on-year. The suppliers get richer whether they expand HBM aggressively or not, which is precisely why they won't rush.
And all three are, in fact, announcing accelerated fab timelines and bigger capex. Yet most forecasts still say the shortage worsens next year. New memory fabs take two to three years to reach production; the incentive to fill them with commodity DRAM rather than HBM persists the entire time.
So the enabler cannibalizes itself. The AI boom created insatiable HBM demand, that demand tightened DRAM broadly, the broad tightening made commodity DRAM more profitable than HBM, and that inversion now discourages the suppliers from fixing the one bottleneck the boom can't live without.
Nvidia's memory diet is the first visible symptom of that loop reaching the customer. The most powerful buyer in tech is trimming its flagship not because it made a design choice, but because someone upstream made a margin choice for it.
The open question is narrow and specific: whether Nvidia ever officially confirms the final Rubin Ultra config, or lets the tested 192GB and 256GB HBM4 options quietly become the shipping reality while the 1TB concept fades into a slide nobody references again.
Watch the wafer allocation, not the keynote. That's where the specs are actually being written.