"Nvidia's Two-Track Memory Strategy Tests Korean Suppliers":
Samsung Electronics is reportedly preparing to route the base dies for Nvidia's custom NVHBM through TSMC's 3nm process — the manufacturing arm of its most direct foundry competitor. Frame that as a procurement decision and you miss it entirely. It is a structural concession: the company that spent years marketing turnkey memory-plus-logic integration is accepting that winning Nvidia's next-generation memory business requires outsourcing the logic layer to a rival.
The base die has reportedly surfaced as a power shift, and per reports the bargaining question has settled in Nvidia's favor.
The base die has reportedly surfaced as a power shift, and per reports the bargaining question has settled in Nvidia's favor.
The reported arrangement is about more than capacity. Samsung, SK hynix and Micron are all expected to build NVHBM base dies on the same TSMC 3nm process, because Nvidia wants manufacturing uniformity across every supplier. That uniformity mandate is self-enforcing. Industry estimates put TSMC's 3nm yield north of 90%, while Samsung Foundry's comparable SF2 2nm technology is thought to be around 60% — estimates, not validated production data, and not directly comparable across nodes and designs, but reportedly enough to suggest a confidence gap underneath Nvidia's decision.
For Nvidia, irregular yields mean higher costs, delayed production, and product certification problems. Standardizing erases the variable.
The deeper break is architectural. HBM memory controllers have always sat on the primary GPU or XPU compute die. NVHBM reportedly moves the controller onto the HBM base die itself, turning that part from a standard interface component into a sophisticated logic device performing memory-control functions. Per reports, the targets: up to 30% more memory bandwidth, 15% less power, and roughly 25% more free area on the main compute die.
Read that last number carefully. Area freed on the accelerator is area Nvidia keeps. Logic moved into the base die is logic Nvidia designs.
So the base die transforms from the memory maker's last proprietary logic layer into a standardized, Nvidia-specified part fabricated by TSMC. Once the controller is Nvidia's and the process is TSMC's, Samsung and SK hynix compete on DRAM core die yield alone — a commodity race with no design sovereignty.
The counterargument writes itself: this is just division of labour, the natural specialization of a maturing supply chain. Independent analyst Damnang makes a version of it, noting that customers and suppliers co-design next-generation HBM and 3D-stacked DRAM, and that switching suppliers would require compatibility work and revalidation. Citrini's Jukan counters that co-design never resolves who absorbs excess inventory if accelerator production falls, illustrating the point with a hypothetical cut from one million units to 800,000.
Both are arguing about the wrong thing. Co-design without design ownership is subcontracting by another name. The flexibility question — whether a co-designed part locks a customer in — presumes the memory maker still holds something proprietary to withhold. Under NVHBM, it doesn't.
Sungkyunkwan University's Kwon Seok-joon has mapped where the value goes. TSMC can capture memory's high-value layers without building a single DRAM plant, he argues, through four routes: base die manufacturing, hybrid bonding stacking and integration leadership, partnering with Taiwanese DRAM makers, and producing 3D DRAM peripheral circuits. None require TSMC to become a memory company.
His prescription is blunt: Korean companies need to become co-designers of the base die. Securing mass production capability in hybrid bonding before TSMC does should be their last line of defense.
That last line is already under pressure. According to Kwon Seok-joon, hybrid bonding is expected to become essential once HBM stacks reach around 20 layers. But TSMC is reportedly delaying investment in hybrid bonding for HBM integration, choosing to keep microbumps inside advanced packages — and preparing its supply chain for 5-micrometer microbumps, with mass production expected in the second half of 2028, per a report citing techpowerup.com. South Korean and Japanese suppliers are reportedly working with TSMC on the smaller interconnects.
The logic is uncomfortable for Seoul. Hybrid bonding is where Samsung and SK hynix might still claim stacking and integration leadership. If TSMC reaches sufficient packaging performance with 5-micrometer microbumps, it never needs to cede that ground.
The two-track framing dominates Korean coverage, and it captures something real. Nvidia is expected to run a dual-bin HBM4 strategy: a top tier at 11.7 Gbps and above, supplemented by a secondary tier in the 10 Gbps range, because no supplier can fill all volume with peak-performance parts. Samsung's HBM4 hits 11.7 Gbps — roughly 46% above JEDEC's 8 Gbps standard, expandable to 13 Gbps — using 1c DRAM and a 4nm base die, at an industry-estimated price around $700, 20% to 30% above HBM3E.
But the two-track strategy is a purchasing tactic. The base die mandate is a structural fact. One is Nvidia managing suppliers. The other is Nvidia redesigning what a supplier is.
Samsung's Taylor Fab 2 arrangement with AMD reportedly shows the same dynamic in a different geography. Samsung reportedly secured orders for the entire planned output, with AMD reportedly accounting for most of the demand, manufacturing HBM base dies for AMD and NVIDIA using a 2nm process, according to industry sources. Even when a memory maker owns the fab, the customer determines the process and the design.
Owning the factory is not the same as owning the decision.
The most likely outcome is not a rupture. SK hynix will keep supplying DRAM core dies. Samsung will keep shipping HBM4. The alliance holds. The balance of power shifts underneath it.
A former SK hynix executive put the endpoint plainly: if Korea's two memory giants fail to take the lead in base dies, bonding and heat treatment as HBM moves to 20 layers or more, they could be reduced to subcontractors that supply nothing but DRAM cells.
That is the mechanism, stated without ornament. Korean memory makers are being asked to fund capacity expansion for a product whose most valuable layer — the controller logic, the process node, the integration step — they do not control.
Kwon's advice is to diversify custom HBM customers — Google, AMD, Meta — and protect design sovereignty outside Nvidia. That is reportedly one version of the business where the memory maker is still a designer.
The dispute between Korean media and analysts misses the point. The question was never whether co-design limits customer flexibility. It is whether memory makers retain any proprietary logic layer at all. On the current trajectory, it is unclear that they do.